Write a task to wait a signal to go high(initially signal is low) within 50ns

SystemVerilog
,
1

one bit signal coming from design, its a pulse kind of signal, Initially signal is low.
write a task to wait a signal to go high within 50ns timeout then end the task, if signal is taking morethan timeout to go high then end the task with timeout error?? Don’t use assertions in task method

2 

task time_out();
 bit a;
 fork
   begin
    @(posedge sig);
    end
   begin
     #50;
     a++;
   end

 join_any
 if(a)
  begin
    $display("TIMEOUT OCCURED");
     a=0;
  end
 else
   $display("PULSE IS DETECTED BEFORE TIMEOUT");
endtask

Reagrds,
Shanthi V A
www.maven-silicon.com

3

In reply to shanthi:

Input is getting always from Design or DUT or DUV
Maybe below code is correct

always @(intf.a) begin
   sig_task(intf.a);
end
task static sig_task(bit a);
if(a==1)begin
   cur_time=$time;
   prev_time=$time;
   if((cur_time-prev_time) <51)begin
     $display("PULSE IS DETECTED BEFORE TIMEOUT");
     $finish
  end
   else
       $display("timeout");
 if (a==0)begin
 prev_time=$time;
 cur_time =0;
 end
endtask