A testbench and a DUT interact with each other.For Interaction with the DUT, the testbench sends a 'valid' signal to the DUT. For Every such 'valid', the DUT will later send an 'ack' signal. Both 'valid' and 'ack' are 1 clock wide pulses, they are active high signals and synchronous to the same clock.
The maximum possible rate of 'valid' is 1 'valid' in 3 consective clock cycles. The maximum possible rate of 'ack' is also 1 'ack' in 3 consective clock cycles. As DUT may take variable amount of time to process the valid sent by testbench the 'ack' from DUT can get delayed. Every 'valid' for which the DUT is yet to send back the 'ack' treated as 'outstanding_valid'
if the number of such outstanding valid exceed 32, then the bench can't drive additional 'valid' till the number of the outstanding valid comes below 32.
please help me in this.