Write an assertion for checking whether global clock is working properly with out taking a relative clock

SystemVerilog
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1

I have been trying to write an assertion for checking whether global clock is working perfectly.
I formulated an idea using a relative clock. How to do it with out the relative clock?

I drop my code with relative clock so that you can get the idea correctly

// gclk is the global clock
// clk is the reference clock

// Assertion for the problem

  property GCLK;
    @(posedge clk) $rose(gclk) @negedge(clk) $fell(gclk);
  endproperty : GCLK
2

In reply to bachan21:
Not clear as to what you mean by checking whether global clock is working properly.
If you mean that checking that it is toggling per required frequency, you can do something like the following:

 
module top; 
    timeunit 1ns/10ps;
     bit g_clk, clk, a, b;  
     global clocking clk_global @(posedge g_clk); endclocking
     default clocking cb_clk @ (posedge clk);  endclocking 
     let half_period=5ns; 
     initial forever #half_period g_clk=!g_clk;  
      
     always  @(posedge g_clk)  begin 
        clk <= ! clk; // derived clk 
     end 
     
    initial begin : b0
      bit got_gclk, done; 
       begin  : f_ever
        fork
          begin : one 
            @(g_clk); 
            got_gclk=1'b1; 
            done=1'b1; 
          end  : one 

          begin : two 
            #(half_period+1); 
            done=1'b1; 
          end : two
        join_none
        wait(done);
        a_gclk: assert(got_gclk); // g_clk is active
        got_gclk=1'b0; 
        done=1'b0; 
      end : f_ever        
    end  : b0

    initial begin 
       #100; 
       $finish;
    end 
 endmodule

Note: assertion: A statement that a given property is required to hold. An assertion is a “statement about a design’s intended behavior” (From Assertion-Based Design, Foster).
It can be written in many forms, SVA is one of them, but there are other approaches.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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3

In reply to ben@SystemVerilog.us:

Thanks for the reply Ben.
I understood your approach.
But my intention is to use SVA to solve this problem.

I will clarify the scenario for you.

I have a clock (Lets call it global clock and take a time period of 10ns).
I want to write an assertion such that it will check clock is maintaining that 10ns time period
4

In reply to bachan21:

My previous assertion checks for activity.
For measurements see examples
https://verificationacademy.com/forums/systemverilog/checking-clock-period-using-system-verilog-assertion
Use realtime and $realtime