Dear Verification experts, i have a question about casting in System Verilog.
suppose there is a base class
class base_transaction extends uvm_sequence_item;
rand bit[7:0] addr, data;
...
endclass: base_transaction
and a derived class
class derived_transaction extends base_transaction;
rand bit[7:0] opcode;
rand int size;
...
endclass: derived_transaction
and handles to both class types
...
base_transaction basep = new;
derived_transaction derivedp = new;
derived_transaction new_derivedp = new;
...
it is legal to assign the ‘derivedp’ to the base pointer. But now using the base_pointer we cannot access ‘opcode’ and ‘size’.
suppose there arises a need to downcast basep to derivedp by doing cast$(new_derivedp, basep) will i be able to access ‘opcode’ and ‘size’ of the transaction using the ‘new_derivedp’ pointer?
or would 'new_derivedp’not be able to access the derived class members since it was downcasted from a base_pointer?