Work around for variable width bit slicing?

SystemVerilog
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1

I am trying to check the fields of the similiar name in all the registers in my reg model by writing all ones and reading back the value.

my_fields = all_fields.find(rx_reg9) with (!uvm_re_match("Rld*",rx_reg9.get_name()));     

                   `read_hreg(rx_reg9,register_data); //user defined macro 
                           for (int i=0; i<my_fields.size(); i++) begin
                               msb = (((my_fields[i].get_n_bits)-1) + (my_fields[i].get_lsb_pos));                            
                               lsb = (my_fields[i].get_lsb_pos);
                               register_data[b][msb:lsb] = ((uvm_reg_data_t'(1) << my_fields[i].get_n_bits)-1);     //concerned line of code
                           end
                   `write_hreg(rx_reg9, register_data)  //user defined macro
                   `read_hreg(rx_reg9,rd_value);

I am seeing this error: Illegal operand for constant expression (since the width in the range operator is not constant).
The problem is that the width of the concerned fields in the registers are NOT CONSTANT. So can anyone suggest a work around for this case

Thanks in Advance :)

2

In reply to saikiran1825:

You can do a bitwise OR

register_data[b] = register_data[b] | ((uvm_reg_data_t'(1) << my_fields[i].get_n_bits)-1) << lsb;