Wildcard import

SystemVerilog
1

I have doubt in following lines from LRM
“Identifiers is imported only when it is referenced in the importing scope and it is neither declared nor explicitly imported into the scope.”
“Similarly a wildcard import of an identifier is overridden by a subsequent declaration of the same identifier in the same scope”

Now I have doubt that if it is wrong to import any identifier from package ,if that identifier is already declared in the importing scope then how subsequent declaration of same identifier will override the imported identifier value.from my point of view ,it should show errors.

2

In reply to SidRaj:

package p;
  bit a,b,c,d;
endpackage
module top;
  wire w,x,y,z;

  import p::a; // explicit import of a
  import p::*; // wilcard import of p. identifers b,c,d are all candidates.
  
  assign x = a; // referes to p::a, it was explicitly imported
  assign y = b; // p::b is now imported
  bit c;  //       p::c is no longer a candidate for import
  // declaring a or b here would be an error since they have already been imported
  // declaring d here would override the wildcard import
  // since we never declarted or referenced d, it is not imported
endmodule
3

In reply to dave_59:

There you mentioned in wildcard import of p "identifiers b,c,d are candidate " , so Is a is not candidate here?

4

In reply to SidRaj:

Correct. ‘a’ has already been explicitly imported.