Why unpacked array is not array is supporting bitwise operation but packed array is supporting bit wise operation

SystemVerilog
1

//--------------------- unpacked array--------------

module m ;
  int a[0:4] ,b[0:4],c[0:4];
  initial 
    begin
      a='{1,2,3,4,5};
      b='{1,3,5,4,2};
      c=a&b;
    end
  endmodule

output:
ERROR VCP5231 “The “”&”" operator cannot be applied to the unpacked array ““a””."
ERROR VCP5231 “The “”&”" operator cannot be applied to the unpacked array ““b””."
//----------packed array----------------

 module g ;
  bit [0:1] f;
  bit [0:1] g;
  bit [0:1] h;
  initial 
    begin
      
      f=2;
      g=3;
      h=f&g;
 $display("h is %d",h);
     end
  endmodule

output
h is 2

1.why in unpacked array getting output error if it is not support bitwise operation what is the reason
can any one clear my doubt .

2

In reply to Om Ganesh B k:

The SystemVerilog LRM defines Boolean operator to work on integral data type values. Unpacked arrays are not integral values. You would have to use a foreach loop ro get the result you are looking for

foreach(c[i]) c[i] = a[i]&b[i];