What is the use of have 4-state data type to time ? How can time be unknown ?
In reply to Sv-hustler:
‘time’ is just a data type. It is possible that a variable with that data type is unassigned, resulting in a value of 'x.
In reply to Sv-hustler:
The time datatype is 4-state because Verilog only had 4-state integers. In Verilog, time and integer were similar types except that their size were platform dependent. SystemVerilog fixed time as a 64-bit unsigned integer, and integer as 32-bits.