In reply to sk7799:
Quote:
what is the correct way of calling the randomize() method and why?
That depends on your verification methodology and your goals. Consider the following possibilities:
- UVM methodology Here your randomize will be in the sequence
class rand_seq extends uvm_sequence #( counter_xactn, counter_xactn );
...
task body();
req = counter_xactn::type_id::create("req");
forever begin
start_item(req);
// The contents of the sequence item are populated between the calls to
// start_item() and finish_item(), either through directed or randomized means.
// assert(req.randomize()); // ** AVIOD THIS
if (!req.randomize()) `uvm_error("MYERR", "This is a randomize error");
//`uvm_info({get_type_name(),":body"},{"Sending transaction ",req.convert2string()}, OVM_MEDIUM)
finish_item(req);
//`uvm_info("rand_seq", "finished_item in task body ovm_low", OVM_LOW)
end
endtask: body
endclass: rand_seq
- A la UVM, but not UVM Here the randomize is in a class, see
https://verificationacademy.com/forums/systemverilog/systemverilog-or-uvm#reply-102209
class simple_random_sequence;
transaction tx=new();
virtual task run();
if (!randomize(tx)) `uvm_error("MYERR", "This is a randomize error");
// if(!randomize(tx)) $error("randomization failure");
endtask : run
endclass : simple_random_sequence
module tb;
...
// test using simple_random_sequence
always @ (posedge clk) begin : random1
..
for (int i=0; i<40; i++) begin : for1
simple_rand_sequence_ld_mostly_hi.run();
data_in <= simple_rand_sequence_ld_mostly_hi.tx.data;
ld <= simple_rand_sequence_ld_mostly_hi.tx.ld;
@ (posedge clk);
end : for1
$finish;
end : random1
- Quick testbench I randomize in the initial statement. I do that to test my assertions
module top;
timeunit 1ns; timeprecision 100ps;
`include "uvm_macros.svh" import uvm_pkg::*;
bit clk, a, b, reset_n;
initial forever #10 clk = !clk;
...
// my assertions her
initial begin
bit v_a, v_b, v_err;
repeat (200) begin
@(posedge clk);
if (!randomize(v_a, v_b, v_err) with {
v_a dist {1'b1 := 1, 1'b0 := 1};
v_b dist {1'b1 := 1, 1'b0 := 2};
v_err dist {1'b1 := 1, 1'b0 := 15};
}) `uvm_error("MYERR", "This is a randomize error");
a <= v_a;
if(v_err==0) b<=v_b; else b<=!v_b;
end
$finish;
end
endmodule
The point, the
if (!randomize .. can be anywhere...
// (edited) anywhere inside a procedural context.
Ben Cohen
http://www.systemverilog.us/
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
...
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- SVA Alternative for Complex Assertions
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