Why randc solution is not cyclic?

SystemVerilog
, ,
1

Hi,

Can someone help to find out this 2 questions:
1.why the randc solution set is not cyclic?
2.how can I constraints to generate even distributed solution in val for given inner_idx[8] & idx[4][2] set?

The solutions of val, defined as randc contain repeated values.

inner_idx:'{'h0, 'h1, 'h2, 'h1, 'h3, 'h0, 'h3, ‘h2} ,val:’{'h0, 'h5, 'h9, 'h4, 'hd, 'h0, 'hc, ‘h8}
inner_idx:’{'h0, 'h1, 'h2, 'h1, 'h3, 'h0, 'h3, ‘h2} ,val:’{'h1, 'h4, 'h8, 'h5, 'hc, 'h1, 'hd, 'h9}

inner_idx:'{'h3, 'h3, 'h2, 'h2, 'h1, 'h1, 'h0, ‘h0} ,val:’{'hc, 'hd, 'h9, 'h8, 'h4, 'h5, 'h1, ‘h0}
inner_idx:’{'h3, 'h3, 'h2, 'h2, 'h1, 'h1, 'h0, ‘h0} ,val:’{'hd, 'hc, 'h8, 'h9, 'h5, 'h4, 'h0, 'h1}

class A;
   bit[3:0] idx[4][2] = '{'{0,1},'{4,5},'{8,9},'{12,13}};
   bit[1:0] inner_idx[8];
   
   randc bit[3:0] val[];

   constraint val_cs {
      val.size() == 8;
   }
   
   constraint idx_cs {
      foreach(val[i]) {
	 inner_idx[i] == 0 -> val[i] inside {idx[0]};
	 inner_idx[i] == 1 -> val[i] inside {idx[1]};  
	 inner_idx[i] == 2 -> val[i] inside {idx[2]};  
	 inner_idx[i] == 3 -> val[i] inside {idx[3]};
      }
   }

   function new();
      foreach(inner_idx[i])
	this.inner_idx[i] = i%4;
      `ifndef ORGIN_ORDER
      inner_idx.shuffle();
      `endif
   endfunction // new

   function void randomize_it();
      this.randomize();
      $display("inner_idx:%p,val:%p",inner_idx,val);
   endfunction // randomize_it
   
endclass // A


module tb;
   A a;

   initial begin
      for(int i=0;i<2;i++) begin
	 a = new();
	 repeat(2) begin
	    a.randomize_it();
	 end
	 $display("");
      end
   end
endmodule
2

In reply to mlsxdx:

randc bit[3:0] val;

your “randc” is for “array”, not for the item inside
that’s why.

I think you want to avoid repetition via randc
in your case, just use this.


   rand bit[3:0] val[];
   constraint val_cs {
      val.size() == 8;
      unique {val};
   }