Why only ##1 (single delay operator) used in the case of multiple clock sequences?

SystemVerilog
,
1

Hi,

My question is related to assertions.

Why ##1 is used when it comes to multiple clock sequences.
What happens if ##2 is used.

Please help me understand.
Thanks in advance.

2

In reply to sk7799:

Multiclocking is allowed after the ##0 or the |-> (same timing effect) and the ##1 or the |=> (same timing effect) See
https://photos.app.goo.gl/gmErFu2ThvZhJaPa8

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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