Why my data is not Printing?

SystemVerilog
1

Dear Sir,
Please help me out in the following code. My data values are not printing and tell me why it is not printing.

module top(); 
	integer value, data; 
	reg [31:0] address; 
initial 
	begin 
		repeat(5) 
			begin 
				#1; 
				value = $random % 10; 
				address = {$random} %10; 
				data = 10 + {$random}%(100-10);
			end 
	end 

initial
$monitor ("data = %0d", data);
initial
$monitor("address = %0d; value = %0d", address,value); 

endmodule
2

In reply to bhar3777:

Hi,

Please refer LRM IEEE Std 1800-2012 ยง section-21.2 Display system tasks .

3

In reply to bhar3777:

There should be only single $monitor in entire simulation. Here you can combine address, value and data in a single $monitor.

$monitor("address = %0d; value = %0d; data = %0d", address,value,data);