Why it's not working on #15 delay

module asertion_ex;
  bit clk=0;
  bit a;
  
  always #5 clk = ~clk; //clock generation
  
  //generating 'a'
  initial begin 
    a=1;
    #15 a=0; // not working 
    //#14 a=0; // is working 
    #10 a=1;
    #10 a=0;
    #10 a=1;
    #10 a=0;
    #10 a=1;
    #10;
  end
  
  //assertion sequence
  sequence seq_1;
   @(posedge clk) a==1;
  endsequence
  
  //calling assert property
  a_1: assert property(seq_1)
      $display("success, time: %0t, a: %0d", $time, a);
    else
      $display("failed,  time: %0t, a: %0d", $time, a);
initial 
begin
	#1000;
	$finish;
end
endmodule

In reply to muku_383:

Issue isn’t with #15.


//1. assertion sample the value in the prepone region and use that value in deciding the outcome of the assertion 
//2. Execution of the pass/fail code of concurrent assertions happen in the re-active region. 
//In between 1 and 2, assignment of the variable a happens.  
// so if you use the $sampled then it will display the value which was used for assertion evaluation. 

a_1: assert property(seq_1)
  $display("success, time: %0t, a: %0d", $time, $sampled(a));
else
  $display("failed, time: %0t, a: %0d", $time, $sampled(a));

I suggest you to go through the SV Scheduling.

In reply to Rahulkumar:

sure sir, thank you

In reply to muku_383:
Need one more help sir,
i want to read random generated text file and send to driver using UVM.

  1. i have random generated signals as:- rq1: 2, rq2: 10, rq3: 22.
    in sequence
  2. open ran_gen.txt file
  3. read first string word from txt file and split into 3 part because, 3 signals are there and i need those 3 to send to driver.
  4. after split need to store into reg and then use `uvm_Send to send it to driver.

is it right step?

In reply to muku_383:

In reply to muku_383:
Need one more help sir,
i want to read random generated text file and send to driver using UVM.

  1. i have random generated signals as:- rq1: 2, rq2: 10, rq3: 22.
    in sequence
  2. open ran_gen.txt file
  3. read first string word from txt file and split into 3 part because, 3 signals are there and i need those 3 to send to driver.
  4. after split need to store into reg and then use `uvm_Send to send it to driver.
    is it right step?

do you mean store into object (transaction class) when you say store into reg (4th point)?

if Yes then this approach looks fine to me.