Why here at least One bin is not creating?

SystemVerilog
, , ,
1 
module simple_cross;
event smpl;

class scross;
  typedef enum {a,e,i,o,u} vowels;
  rand vowels v;
  bit inactive = 1;
  rand bit[2:0] cnt;

  covergroup cg @(smpl);
      a: cross cnt, v iff (inactive);   
  endgroup

  function new();
    cg = new();
  endfunction
endclass

scross sc = new();

initial
  for (int i=0; i<100; i++) begin
    void'(sc.randomize());
    -> smpl;
  end

endmodule


Here firstly I have given a delay before the smpl event like

initial
for (int i=0; i<100; i++) begin
void’(sc.randomize());
#5;
→ smpl;
end

Then the bins are created. but If I remove the delay then single bin is not creating. I expect if there is no delay the for loop will run for 100 times in 0th simulation time. But the smpl event will be triggered for at least for one time(what I expect). Please correct me if there is any misconception.

2

In reply to Subhra Bera:

You will always run into trouble trying to generate events with 0 delay and at time 0. You would be much better off calling the corergroup’s sample() method.

The SystemVerilog LRM does not say much about how different constructs behave at time 0. It’s possible the events trigger before the process that gets set up waiting for the trigger.