Why first_match does not work?

SystemVerilog
, ,
1

Hi,

I have came cross a SVA issue on using first_match.

//The assertion is intend to do the following check
//-----------------------------------------------------------------------------------------------------------
//when the first sub_int asserted if int_en is enabled, within 1~5 clk, merged_int will be asserted
//sub_int may assert mutiple times before merged_int asserted

   property sub_int_int_s;
      @(posedge clk)
     first_match($rose(sub_int) ##0 int_en) |-> ##[1:5] $rose(merged_int);
   endproperty // sub_int_int_s

   P_SUB_INT_INT_S: assert property (sub_int_int_s);

Somehow, the first_match doesn’t filter out non-first $rose(sub_int).
Can someone help me figure it out what problem is here?

2

In reply to mlsxdx:

you are probably looking for


$rose(sub_int) && (!merged_int) && int_en |-> ##[1:5] $rose(merged_int);
3

In reply to mlsxdx:

https://verificationacademy.com/forums/systemverilog/clarification-firstmatch#reply-43005

4

In reply to ssureshg_:

Thank you. That is exactly what I am looking for. :-)

5

In reply to dave_59:

Thanks for your quick reply, Dave. I will study the post again.