Why drive task is not excuting & simulation not stoping please tell me

SystemVerilog
1 


`ifndef tsp_driver
`define tsp_driver
`include "trans_if.sv"
`include"tsp_trans.sv"

class tsp_driver;

virtual trans_if.DR wif;

tsp_trans data2duv;

mailbox#(tsp_trans) gen2dr;

function new( virtual trans_if.DR wif,
              mailbox#(tsp_trans) gen2dr);

this.wif=wif;
this.gen2dr=gen2dr;
this.data2duv=new;
endfunction


virtual task drive();
@(wif.dr_cb);

begin
wif.dr_cb.DMA_RQST<=data2duv.DMA_RQST;

wif.dr_cb.data_in<=data2duv.data_in;

wif.dr_cb.addr_reg<=data2duv.addr_reg;

wif.dr_cb.data_link_in<=data2duv.data_link_in;

wif.dr_cb.LINK_DMA_ABORT<=data2duv.LINK_DMA_ABORT;

wif.dr_cb.link_fis_recved_frm_dev<=data2duv.link_fis_recved_frm_dev;
wif.dr_cb.phy_detect<=data2duv.phy_detect;

wif.dr_cb.H_write<=data2duv.H_write;

wif.dr_cb.H_read<=data2duv.H_read;

wif.dr_cb.link_txr_rdy<=data2duv.link_txr_rdy;

wif.dr_cb.r_ok<=data2duv.r_ok;

wif.dr_cb.r_error<=data2duv.r_error;

wif.dr_cb.illegal_state<=data2duv.illegal_state;

wif.dr_cb.end_status<=data2duv.end_status;

wif.dr_cb.DMA_TX_DATA_IN<=data2duv.DMA_TX_DATA_IN;

wif.dr_cb.DMA_TX_WEN<=data2duv.DMA_TX_WEN;

wif.dr_cb.DMA_RX_REN<=data2duv.DMA_RX_REN;

wif.dr_cb.VALID_CRC_T<=data2duv.VALID_CRC_T;

wif.dr_cb.data_out_vld_T<=data2duv.data_out_vld_T;

wif.dr_cb.CRC_ERR_T<=data2duv.CRC_ERR_T;

wif.dr_cb.DMA_INIT<=data2duv.DMA_INIT;

wif.dr_cb.data_link_rd_en_t<=data2duv.data_link_rd_en_t;

wif.dr_cb.PIO_CLK_IN<=data2duv.PIO_CLK_IN;

wif.dr_cb.DMA_CLK_IN<=data2duv.DMA_CLK_IN;

wif.dr_cb.CE<=data2duv.CE;

wif.dr_cb.RX_FIFO_RESET<=data2duv.RX_FIFO_RESET;

wif.dr_cb.TX_FIFO_RESET<=data2duv.TX_FIFO_RESET;



data2duv.display("================ INPUT_DATA_DERIVED_BY_DRIVER-=================");
end
endtask 




virtual task start();
fork
     forever
     begin
           gen2dr.get(data2duv);
           $display("QQQQQQQQQQQQQQQQQQQQQQQQQQ");
           drive();
           
     end
join_none
endtask
endclass
`endif
2

In reply to uvm_verification:

You dont stop once you call start do you… Doesnt seem like there is a way to stop from your code. Probably the reason why simulation never ends.
Also, I dont see a need for fork join_none in your start. Serves no purpose by the looks of it.

3

In reply to kernalmode1:

Who calls start()? Where is your run_phase() task?

4

In reply to dave_59:

In reply to kernalmode1:
Who calls start()? Where is your run_phase() task?

this is my environment class here i call start(); methods of all the lower level classes (generator,driver,write_monitor,read_monitor,refrence model, scoreboard),

i am not getting what is wrong



`ifndef tsp_env
`define tsp_env

`include"trans_if.sv"
`include"tsp_trans.sv"
`include"tsp_gen.sv"
`include"tsp_driver.sv"
`include"tspw_monitor.sv"
`include"tspr_monitor.sv"
`include"tsp_model.sv"
`include"scoreboard.sv"

class tsp_env;

virtual trans_if.DR wif;
virtual trans_if.WR_MON wmonif;
virtual trans_if.RD_MON rmonif;

mailbox#(tsp_trans) gen2dr=new();
mailbox#(tsp_trans) wmon2ref=new();
mailbox#(tsp_trans) rmon2sb=new();
mailbox#(tsp_trans) ref2sb=new();



function new(virtual trans_if.DR wif,
             virtual trans_if.WR_MON wmonif,
             virtual trans_if.RD_MON rmonif);
 
this.wif=wif;
this.wmonif=wmonif;
this.rmonif=rmonif;

endfunction



tsp_gen gen;
tsp_driver drv;
tspw_monitor wmon;
tspr_monitor rmon;
tsp_model model;
scoreboard sb;


task build();

gen=new(gen2dr);
drv=new(wif,gen2dr);
wmon=new(wmonif,wmon2ref);
rmon=new(rmonif,rmon2sb);
model=new(wmon2ref,ref2sb);
sb=new(ref2sb,rmon2sb);
endtask

task start();
gen.start();
drv.start();
wmon.start();
rmon.start();
model.start();
sb.start();
endtask

task stop();
		wait(sb.DONE.triggered);
	endtask : stop 


task run();

	  	start();
              $display("=======================ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");

		stop();
		sb.report();

endtask

endclass 
`endif
5

In reply to uvm_verification:

I think the issue is “this.data2duv=new;” inside function new(). Since you are just getting the packets through mailbox, for that you need not require to give memory to the handle data2duv.

6

In reply to uvm_verification:

You are essentially reinventing the UVM. You will need to improve your debugging skills and learn to figure how your code gets executed.

7

In reply to kernalmode1:

In reply to uvm_verification:
You dont stop once you call start do you… Doesnt seem like there is a way to stop from your code. Probably the reason why simulation never ends.
Also, I dont see a need for fork join_none in your start. Serves no purpose by the looks of it.

i didnt create memory for (data2duv=new) than also simulation not stopping.

8

In reply to uvm_verification:


//simulation is hanging : 

//are you seeing this display statement in run log ? 
//if not then your simulation is stuck inside the start() call
task run();
	  	start();
$display("=======================ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ");
		stop();
		sb.report();
endtask


//if it is stuck inside the start() call then check start method of each component.
//None of these call shouldn't block the simulation
task start();
gen.start();
drv.start();
wmon.start();
rmon.start();
model.start();
sb.start();
endtask



//if you are seeing the display statement after the start then it might be blocked inside the stop method due to wait statement. 
task stop();
		wait(sb.DONE.triggered);
endtask : stop 


//Just to finish the simulation, add some timeout logic similar to uvm
initial begin
   #100us;  // add this based on your test run time
   $error("timeout occurred, finishing the simulation");
   $finish;
end



//drive method isn't executing :

//are you seeing this display statement in the run log.
//if not then get method isn't getting any transaction from mailbox because it is empty.
//Hence it won't come out of the get call and won't execute the drive method. 

virtual task start();
fork
     forever
     begin
           gen2dr.get(data2duv);
           $display("QQQQQQQQQQQQQQQQQQQQQQQQQQ");
           drive();
 
     end
join_none
endtask
endclass