In reply to Shawn Zhang:
SystemVerilog is foremost a Hardware Description Language (HDL). "Hardware" in this case is a discrete digital abstraction of continuous analog voltages, currents, and billions of devices operating concurrently. Everything is executing in parallel, there is no single "main" entry point like there is in software.
Simulation of hardware is using software to model hardware. An HDL gets compiled onto a host hardware platform for simulation, and that host hardware has nothing to do with the hardware being modeled. The host hardware platform may take hours to simulate what occurs in seconds on the hardware being modeled. The "simulation time" represents the time in the hardware model. It is different abstraction from the time it takes host hardware to execute the model.
A "test" can be considered software; it has a main entry point. In the UVM, that entry point is called by the task run_test().
Only one piece of SystemVerilog, its Object Oriented class system, comes from Java. Actually it comes indirectly from another language "Vera" whose class system came from Java. Both Java and Vera were developed at Sun Microsystems, hence the connection.