Why doesn't Systemverilog need a 'main' function like Java?

SystemVerilog
1

I know SV has an ‘initial’ keyword to mark the 0 time of the simulation time of the program.
I know UVM is designed by using SV and the entry of a UVM test case is the ‘run_test()’.
I also heard that SV language is designed by using Java as a prototype.

Then, come this curiosity,

  • Why doesn’t Systemverilog needSystemverilogction like Java?
  • What’s the difference between the ‘simulation time’ of SV with the ‘runtime’ of Java?

Regards
Shawn

2

In reply to Shawn Zhang:

SystemVerilog is foremost a Hardware Description Language (HDL). “Hardware” in this case is a discrete digital abstraction of continuous analog voltages, currents, and billions of devices operating concurrently. Everything is executing in parallel, there is no single “main” entry point like there is in software.

Simulation of hardware is using software to model hardware. An HDL gets compiled onto a host hardware platform for simulation, and that host hardware has nothing to do with the hardware being modeled. The host hardware platform may take hours to simulate what occurs in seconds on the hardware being modeled. The “simulation time” represents the time in the hardware model. It is different abstraction from the time it takes host hardware to execute the model.

A “test” can be considered software; it has a main entry point. In the UVM, that entry point is called by the task run_test().

Only one piece of SystemVerilog, its Object Oriented class system, comes from Java. Actually it comes indirectly from another language “Vera” whose class system came from Java. Both Java and Vera were developed at Sun Microsystems, hence the connection.

3

In reply to dave_59:

Hi Dave,
Exactly what I am looking for! Your reply enlighten me as always!
Regards
Shawn

4

In reply to dave_59:

Hi Dave,

A further query about the difference of interface between java with SV.

I know that ‘interface’ along with ‘implements’ is one of the key concepts of OOP in Java.
It helps to achieve the abstraction and encapsulation of OOP.

However, it looks like ‘interface’ in SV is commonly used to declare the ports of a hardware.
I think the ‘interface class’ in SV is the one equal to ‘interface’ in Java. However, it seems to be not much used (as far as I know).

Above are just my immature thoughts.

  • Could you explain that in your vision?
  • Should we use more more OOP, more design pattern just like software in our tb design to achieve the performance goals such as abstraction, encapsulation reusability, extensibility etc?
  • I know UVM is leveraging many design patterns which makes UVM itself more OOP. However, even we used UVM to build up the project testbench, when there is a new project, copy/paste and modify the ‘class’ directly is more common than leverage OOP features such as override, inheritance, polymorphism.

Regards
Shawn

5

In reply to Shawn Zhang:

A predicament SystemVerilog has is it tries to avoid adding new keywords to keep code backward compatible. The keyword interface was a design construct for port connections long before interface class was added to the language in 1800-2012. You do not see much use of interface classes because it is relatively new and much of the UVM was already implemented before its introduction. But there are a growing number of examples and papers using it.

Regarding OOP versus copy/paste, that remains an educational concern. The majority of hardware design and verification engineers do not have a strong software programming background with OOP and this seems difficult to pick up once you have already started your career.

6

In reply to dave_59:

Make sense. Thanks!
Regards
Shawn