Example, Blocking assignments evaluate their RHS
expression and update their LHS value without interruption. The blocking assignment must
complete before the @(clk) edge-trigger event can be scheduled. By the time the trigger event
has been scheduled, the blocking clk assignment has completed; therefore, there is no trigger
event from within the always block to trigger the @(clk) trigger.
module osc1 (clk);
output clk;
reg clk;
initial #10 clk = 0;
always @(clk) #10 clk =~clk; //Note I have intentionally made it to blocking
initial
begin
#200;
$finish;
end
initial
begin
$monitor($time,"clk %0b ",clk);
end
initial
begin
$dumpvars;
$dumpfile("dump.vcd");
end
endmodule
Note:
The clk signal is driven to 0 at 10ns. but after that it remains in logic 0 till the end of the simulation