Why #delay in a systemverilog class does not take effect?

SystemVerilog
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1

I add #2000ns in my class(actually it’s a UVM test sequence), but it seems that it does not delay 2000ns, I print time before and after this delay, and find that the actual delay is 200ns. And I add a $printtimescale task in this class, then in my log it print:
“TimeScale of $unit is 100 ps / 100 ps”

My question is:

  1. I add timescale in my tb_top.sv: `timescale 1ns/1ps, and I add " -timescale=1ns/1ps " option to my my simulation tool. Why in my class, timescale is 100ps/100ps ?
  2. When I add #2000ns in class, why not 2000ns is delayed? It seems that it treat this sentence as “#2000”, and add 100ps unit, so the result is 2000 * 100ps = 200ns.

Hope somebody can help me, thanks very much!

2

I know its too late (almost 1.5 yrs!!!) to reply to this question, but if available can you please post the code? We can help if you provide some code.

  • Ashith