Why is @(count) not displaying the change in data properly

SystemVerilog
1

Hi all,
This my first post for SystemVerilog code. Being a beginner I have written a simple code for counter and I want to display the start_time and end_time for each count data, more precisely I am trying to monitor the change and get the start and end time for that particular data.
The issue that I am facing is that “@(count)” is skipping the display of “count=01” and directly displaying “count=10” after “count=00”. Is there anything wrong with the coding constructs. Any solution will be of great help.

Please see the code and results of simulation below:


module counter(
  input  logic clk,
  input  logic rstn, 
  input  logic start,
  output logic[1:0] count
);
  
  logic[1:0] prev_count;
  time start_time;
  
  
  
  always @(posedge clk)begin
    if (rstn)begin
      count <= '0;
    end 
    if(start)begin
      	count = count + 1;
      	
     end else begin
        count = count;
        
      end
    end
 
  
  always @* begin
      prev_count = count;
      start_time = $time;
    @(count)
      $display("count= %b\t", prev_count, "<start_time=%0t\tend_time=%0t>", start_time,$time);
  end
  
endmodule

The solution as of now is:
xcelium> run
count= 00 <start_time=0 end_time=10>
count= 10 <start_time=20 end_time=40>

2

In reply to random_coder:

The @* is effectively @count, so it takes two changes to count for every $display. That means you will skip displaying every other change in count.

Realize that the end_time of the previous count is the same time as the start_time for the next count. So you probably should just print the start_time and count with

 always @count
      $display("count= %b\t", time=%0t", count,$time);

BTW, in your first always block, you should not be mixing blocking = and non-blocking <= assignments to the same variable. In a synchronous block, you should only be using <= assignments. And you should not have that else branch count=count;. That is a bad habit. You should let your synthesis tool figure out what needs to be retained.