Why can't we declare and assign a logic type in one step?

SystemVerilog
,
1

We can declare and assign a wire in one step in SystemVerilog.

wire y_and = a & b;

But for logic it does not work.

logic y_and = a & b;

Why is this so? I always thought we can use logic instead of wire or reg in SystemVerilog.

2

In reply to Shashank V M:

I encounter no issues using ‘logic y_and = a & b;’.

You will need to post a complete example which demonstrates your issue.

3

In reply to cgales:

In reply to Shashank V M:
I encounter no issues using ‘logic y_and = a & b;’.
You will need to post a complete example which demonstrates your issue.


module logic_gates(
  input a, 
        b, 
  output y_and             
);
  logic y_and_l = a & b;
  assign y_and = y_and_l;
  
endmodule

Try it on EDA Playground: https://edaplayground.com/x/Cfcu

4

You can declare and assign a logic type with constants on the right hand side, but not with variables.

Sure you can. You just showed it in your EDA Playground example.

5

In reply to sbellock:

For the variable logic type isn’t the assignment in the deceleration just an initializer? Not a shortcut for a deceleration and continuous assignment in one step (as it is with the wire)?

So while syntactically correct, one is not going to get the expected result with the logic - i.e. it’s not going to be a continuous assignment.

6

In reply to Shashank V M:

The difference is in the timing of of the assignment on the RHS.

When declaring a wire the RHS represent a continuous assignment.

wire y_and = a & b;
// above is a shortcut for below
wire y_and;
assign y_and = a & b;

But when declaring a variable, the RHS represent a procedural initialization assignment, and that assignment happens once at the begining of the life of that variable. For static variables, that happens once before time 0. For automatics, the assignment happens once when the entering the procedural block.

function automatic a();
  int x=0;
endfunction
// above is a shortcut for below
function automatic a();
  int x;
  x=0;
endfunction
1 Like
7

In reply to Mark Curry:

Right, but the pattern of both declaring and assigning to a logic variable does have its uses. For instance as a temporary variable in an always block.

always_comb begin
   automatic logic temp_variable = // a ton of expressions that you don't want to repeat over and over.
.
.
end