Why can't I use an interface member in a specify block?

Given the code below:


module timing_checks ( some_interface s_if);

   specify 
      $recovery(posedge s_if.INTERFACE_SIGNAL, posedge s_if.ANOTHER_INTERFACE_SIGNAL, 100us);
   endspecify                      
                          
endmodule 

I continue to get an error message:

(vlog-13069) …/Top/timing_checks.sv(9): near “.”: syntax error, unexpected ‘.’, expecting ‘,’

Can I not use interface members inside specify blocks?

In reply to ce_2015:

Specify blocks cannot have hierarchical references. You have to create a separate module and connect it up to the interface ports, then put your timing check inside that module. SystemVerilog never properly integrated interfaces with specify blocks in the LRM.

In reply to dave_59:

Thank you for the clarification Dave. There’s my suggestion then for the next LRM revision: integrate interfaces with specify blocks :)