Why bit is taking signed value?

SystemVerilog
, ,
1

in the following constraint based randomisation, queue is a bit [2:0] data type which is clearly unsigned but if we see the contents of queue after randomising and inserting into it, it has signed values whis is bit[2:0] storing signed values?

class my_descriptor;
  rand bit [63:0] data;
  rand bit[2:0] mem_id;
 
  bit [2:0] prev_mem_id[$:5];  //Limit queue size
 
 constraint c1{
    foreach(prev_mem_id[i]){
      mem_id != prev_mem_id[i];
    }
  }
  constraint c2{
		mem_id inside {[0:7]};
	};
	
 
 function void post_randomize();
   prev_mem_id.push_back(mem_id);
//$display("----------------------------------------");
//$display(mem_id);
   // prev_mem_id.push_front(mem_id);

//$display("----------------------------------------********");
  endfunction
endclass

module randc_type;


my_descriptor  obj;

initial begin 
obj = new;
//obj.c1.constraint_mode(0);
repeat(5) begin 
obj.randomize();
$display(obj.mem_id);
$display("curernt queue elements are ",obj.prev_mem_id);
end


end
endmodule

The result obtained in QuestaSim is 
# 3
# curernt queue elements are 3
# 7
# curernt queue elements are 3 -1
# 5
# curernt queue elements are 3 -1 -3
# 4
# curernt queue elements are 3 -1 -3 -4
# 2
# curernt queue elements are 3 -1 -3 -4 2
2

In reply to rakesh reddy:
You need to use the format specifier %p or %0p when printing an aggregate type. Or you can use a loop(for or foreach) to print each element of an array.