Why assertion not finished

SystemVerilog
,
1

I have written an assertion as follows, to assert the duty cycle of the clock. When the simulation ended, the tool prompted “a_duty_chk:start at xxxxfs not finished”. I want to know if there is a problem with my writing that caused the assertion to not end normally.


   property duty_chk;
        realtime    duty_chk_start;
        real        duty_h;
        @(posedge clk_out) disable iff((!check_en)||(!clk_en))
            (1, duty_chk_start = $realtime()) ##0 
            @(negedge clk_out) (1, duty_h = $realtime() - duty_chk_start) ##0 
            @(posedge clk_out) ((duty_h/($realtime()- duty_chk_start)<=0.5)&&(duty_h/($realtime()- duty_chk_start)>=0.3);
    endproperty
    a_duty_chk: assert property(duty_chk);
2

In reply to jianfeng.he:
Not finished because sim finished after it was attempted and did not receive the posedge clk_out.
Ben Cohen
Ben@systemverilog.us
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3

In reply to ben@SystemVerilog.us:
Thank you for your help, Ben