Why am i not able to increase the size of dynamic array

SystemVerilog
,
1

this is my code

module arrays();
 int a[];
 bit [7:0]b[];
initial begin
  a=new[20];
  b=new[5];
  $display("%d %d",a.size,b.size);
  a='{1,2,3,5,4};
  foreach(b[i]) begin
  b[i]=i;
  $display("b[%d]=%d",i,b[i]);
  end
  
  foreach(a[i]) begin $display("a[%d]=%d",i,a[i]);end
  $display("........memory reallocation........");
  a=new[10](a);
 $display("size=%d",a.size);
end

endmodule

this is my output

20           5
# b[          0]=  0
# b[          1]=  1
# b[          2]=  2
# b[          3]=  3
# b[          4]=  4
# a[          0]=          1
# a[          1]=          2
# a[          2]=          3
# a[          3]=          5
# a[          4]=          4
# ........memory reallocation........
# size=         10
2

In reply to bellamarigo:

In reply to bellamarigo:

Is it possible for you to also add what output you are expecting? I’m asking because the size of the array ‘a’ has increased to 10 from 5 and you’ve also retained the previous elements.

Just for better understanding, I’ve added some display statements.

Go through the code:

module arrays();

	int a[];
	
	bit [7:0]b[];
	
	initial

		begin
			
			a=new[20];

			b=new[5];

			$display("\nsize of a = %0d, size of b = %0d",a.size,b.size);
			
			a='{1,2,3,5,4};
			
			$display("\nsize of a after initialization = %0d",a.size);
			
			foreach(b[i])

				begin
					
					b[i]=i;
								
				end
				
			$display("\nb = %0p",b);
	
			$display("size of b after initialization = %0d",b.size);

			foreach(a[i])

				begin

					continue;
					
				end
				
			$display("\na = %0p",a);
				
			$display("size of a after foreach display = %0d",a.size);
	
			$display("\n........memory reallocation........");

			a=new[10](a);
			
			$display("\na = %0p",a);
		
			$display("size of a = %0d",a.size);

		end

endmodule