Dear friend,
I have 2 question regarding to the Synthesis.
First,
Can anyone specify that which SystemVerilog syntax can be synthesized?
As an example, I want to know that the following line can be synthesized?
parameter g = 7'b5;
Second,
What is the difference between the parameter and reg from the synthesis point of view? While both store a value. Register can be modified but parameter is constant. Is there anything else?
regards,
I will answer your second question.
Parameter is a constant and remain constant throughout the execution but it is not the case in reg.
The size of parameter is 32-bit by default and in case of reg we can decide its size.
Parameter cannot be synthesized. It is just another way of representation. In your example, to make the value 7’b5 easier to read in the code, then it can be represented in another way by using a parameter called g… It is used for easier coding purposes.
In reply to Reuben:
Thank you for your reply.
So if I use parameter syntax, it would not work in FPGA. right?
In reply to Mahdiyar:
In reply to Reuben:
Thank you for your reply.
So if I use parameter syntax, it would not work in FPGA. right?
Parameters can be used in RTL design and of course it’ll work on FPGA. Basically parametes synthesizes to “wires connected to VDD/GND”.
In reply to Mahdiyar:
This is really not the right forum for discussing synthesis. You should check with the vendor of your tool, they probably have documentation on what SystemVerilog they support. In a perfect world, every SystemVerilog construct could be synthesizable, but most tools have a common subset.
Parameters are like constants, but they can be overridden on an instance basis. You need to look for some basic Verilog training on parameters. In SystemVerilog, parameters can also be types as well as values. I’m not sure all synthesis tools support that yet.
SystemVerilog replaces the keyword reg with logic. Not everything declared as a reg in Verilog becomes a Register.