Please provide applications of synchronous and asynchronous reset.
It is well known that Synchronous reset is preferred for fast circuits, so please try to be as specific as possible.
In reply to venkata-srikanth:
I won’t directly answer the homework question, but I start by correcting part of the problem statement: “It is well known that Synchronous reset is preferred for fast circuits…”
This isn’t even true, at all. There are SOME technologies that, due to implementation shortcomings, prefer synchronous resets over asynchronous resets when one only views certain quality of implementation results as the only metric that matters. (Some FPGA families, cough X)
There are other metrics that one should consider when choosing async vs. sync resets. That’s part of the problem the professor is trying to get one to learn in asking this question.
In reply to Mark Curry:
Upon power-up, it is important to have all mission-critical registers in the benign state since they can potentially activate a mission subsystem, like the launch of a missile!
Upon power-up, it takes some time before the clocks in a subsystem before the clocks become stable. Thus, an asynchronous reset before any clock activation is preferable.