When the values are sampled in the cover group when arguments are passed

Hi ,

could you please let me know when the expression position & vector is checked in the below code. is it only when the constructor of cover group called or each time when ever sample function of cover group called.


covergroup cgmaskbit(input bit [31:0] position, ref bit [31:0] vector);
  pos: coverpoint (position & vector) !=0;
  option.per_instance = 1;
endgroup
 
cgmaskbit cgmaskbits[32];
 
foreach (cgmaskbits[i]) cgmaskbits[i] = new(1'b1<<i,m_csr_intr_mask.interrupting_csrmask);


In reply to srbeeram:

yes, when the sample() function is called.
Here is an example from my SVA Handbook 4th Edition, 2016


module coverx;
    bit clk, smpl;
    logic[3:0] a=4'b1XZ0;
    initial forever #10 clk=!clk; 
    always @ (posedge clk)  begin : aly 
        smpl <= 1'b1; 
        t_cg.sample();   // <-----------------------------The sample of t_cg
        @ (posedge clk);
        smpl <= 1'b0; 
        a=4'b0010; 
    end  : aly

    // If cp_a coverage is ture, then an X or a Z was observed
    cp_aXZ: cover property(@ (posedge clk iff smpl) $isunknown(a)); 
    ap_aNoXZ: assert property(@ (posedge clk iff smpl) $isunknown(a)==0); 

    function automatic int countbits(logic[3:0]  v);
        automatic int s=0;
        for (int i=0; i<= 3; i++) begin 
            if (v[i]===1'bX || v[i]===1'bZ) begin
                s=s+1;
                $display("is X or Z"); 
            end
        end
        $display("%t v=%b, countbits=%d", $time, v, s);
        return s; 
    endfunction : countbits

    covergroup a_is_x_cg;
        type_option.merge_instances = 0;
        option.per_instance = 1;
        option.get_inst_coverage = 1;
        cp_unknown: coverpoint $isunknown(a)==0; 
        // ($isunknown ==0) i.e. true then no X or Z 
        cp_with_countbits:  coverpoint countbits(a) ==0 ; 
        cp_with_countbits_axz:  coverpoint $countbits (a, 'x, 'z) ==0; // 1800-2012 
        // ($countbits (a, 'x, 'z) ==0) then no X or Z 
    endgroup
    a_is_x_cg t_cg = new; // instantiation of covergroup  <<---------------------------

endmodule : coverx 

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr


In reply to ben@SystemVerilog.us:

Thanks Ben for providing the clarification.