When two events are scheduled for the same timeslot

SystemVerilog
1

Hi
Simulating the following block of code:


fork
	begin
	  repeat(4) begin
		#1;
		`uvm_info("Test", $sformatf("seq_1.start"), UVM_LOW)
	  end
	end
	begin
	  repeat(4) begin
		#2;
		`uvm_info("Test", $sformatf("seq_2.start"), UVM_LOW)
	  end
	end
	begin
	  repeat(4) begin
		#3;
		`uvm_info("Test", $sformatf("seq_3.start"), UVM_LOW)
	  end
	end
	begin
	  repeat(4) begin
		#4;
		`uvm_info("Test", $sformatf("seq_4.start"), UVM_LOW)
	  end
	end
join

I got the following output results:


# UVM_INFO top.sv(226) @ 1: uvm_test_top.m_sequencer@@m_seq [Test] seq_1.start
# UVM_INFO top.sv(232) @ 2: uvm_test_top.m_sequencer@@m_seq [Test] seq_2.start
# UVM_INFO top.sv(226) @ 2: uvm_test_top.m_sequencer@@m_seq [Test] seq_1.start
# UVM_INFO top.sv(238) @ 3: uvm_test_top.m_sequencer@@m_seq [Test] seq_3.start
# UVM_INFO top.sv(226) @ 3: uvm_test_top.m_sequencer@@m_seq [Test] seq_1.start
# UVM_INFO top.sv(244) @ 4: uvm_test_top.m_sequencer@@m_seq [Test] seq_4.start
# UVM_INFO top.sv(232) @ 4: uvm_test_top.m_sequencer@@m_seq [Test] seq_2.start
# UVM_INFO top.sv(226) @ 4: uvm_test_top.m_sequencer@@m_seq [Test] seq_1.start
# UVM_INFO top.sv(238) @ 6: uvm_test_top.m_sequencer@@m_seq [Test] seq_3.start
# UVM_INFO top.sv(232) @ 6: uvm_test_top.m_sequencer@@m_seq [Test] seq_2.start
# UVM_INFO top.sv(244) @ 8: uvm_test_top.m_sequencer@@m_seq [Test] seq_4.start
# UVM_INFO top.sv(232) @ 8: uvm_test_top.m_sequencer@@m_seq [Test] seq_2.start
# UVM_INFO top.sv(238) @ 9: uvm_test_top.m_sequencer@@m_seq [Test] seq_3.start
# UVM_INFO top.sv(244) @ 12: uvm_test_top.m_sequencer@@m_seq [Test] seq_4.start
# UVM_INFO top.sv(238) @ 12: uvm_test_top.m_sequencer@@m_seq [Test] seq_3.start
# UVM_INFO top.sv(244) @ 16: uvm_test_top.m_sequencer@@m_seq [Test] seq_4.start

If I want to justify that @2, first “seq_2.start” is displayed and then “seq_1.start” is displayed after it, I would say that although both of these expressions are scheduled to be displayed during the timeslot at 2, “seq_2.start” is actually scheduled first, namely, at the start of simulation when the value of time is 0, while “seq_1.start” is scheduled later, when the value of time is 1. When the simulator reaches the timeslot at 2, it executes the events scheduled for that timeslot in a FIFO order, therefore, “seq_2.start” is displayed before “seq_1.start”.
Is my justification correct?
Thanks in advance
Farhad

2

In reply to Farhad:

The IEEE 1800-2017 SystemVerilog LRM section 4.7 says active events can be executed in any order. There is no guaranteed FIFO ordering. What you see is an observation and cannot be justified. Implementations are free to modify the ordering and do so as a result of optimizations.