property p_max_time(clk,master_rise,slave_rise,duration);
time start_time;
@(posedge clk) ($rose(master_rise),start_time = time) |-> [*0:] $rose(slave_rise) ##0 (($time -start_time) == duration);
endproperty
assert property p_max_time (clk, master_en,slave_ack ,143ns);
In reply to srirahulch95:
Time should be in number of clock cycles, not in ns.
Let max_cycles=20;
ap_max: assert property(
@(posedge clk) $rose(master_rise) |-> ##[1:max_cycles] $rose(slave_rise));
Ben systemverilog.us
In reply to ben@SystemVerilog.us:
In reply to srirahulch95:
Time should be in number of clock cycles, not in ns.
Let max_cycles=20;
ap_max: assert property(
@(posedge clk) $rose(master_rise) |-> ##[1:max_cycles] $rose(slave_rise));
Ben systemverilog.us
Looks like his intention is to check if the delay between slave_rise and master_rise is equal to the expected duration.
In that case he should use ##[0:] instead of [*0:].
Below code should serve the intention.
property p_max_time(clk,master_rise,slave_rise,duration);
time start_time;
@(posedge clk) ($rose(master_rise),start_time = $realtime) |-> ##[1:$] $rose(slave_rise) ##0 (($realtime -start_time) == duration);
endproperty
Regards,
Manju
https://www.linkedin.com/in/manjubhat/
In reply to mbhat:
SVA is based on clocking events. In the above example, if the clock period is 100ns and duration is anything other than an integral of the 100ns period (e.g., 4.8* 100ns, or 4800ns) then the assertion will fail. You can argue that one must limit that duration must be an integral of the period, such as 5 times the period. In that case, you must as well use the max_cycles.
I strongly believe that since SVA is events-based, there is no need to use time in the assertion unless one need to measure, in $realtime, the time between events.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
In reply to ben@SystemVerilog.us:
Hi Ben,
I totally agree to this. I did not think in that perspective.
Thank you.