What's the difference between define and paramter

SystemVerilog
1

In the systemverilog code, is there any difference between ‘parameter’ and ‘define’ ?

for example I have below code. Are they the same when we use them ?


parameter MASTER = 1;
parameter SLAVE  = 2;



define MASTER 1
define SLAVE  2
2

In reply to zz8318:

It depends.

See EDA Software, Hardware & Tools | Siemens Software, especially the part about the Yin.