While designing verilog/ sv, what was the need of comming up with both task and function? Is there any unique uses of them? googling task vs function will give list of differences which every one knows. But why did the designers of verilog/sv language did not merge them into one?
This question is bugging me since long time. Anyone please clear it for me.
In reply to Suhas BV:
Historically, computer languages like Fortran and C are sequential and do not have the concept of concurrency. In languages, like any speaking languages, words have connotations (and politicians have learned that, sometimes the hard way :) ). I believe that by maintaining a single keyword function to express concurrent and non-concurrent actions would have been confusing because when you make that call you lose it implications. Historically, function has the implication of non-sequentiality. Thus, I can understand the need for a different keyword (like task) to clarify the intent; this creates good programming practices.
Ben SystemVerilog.us
In reply to Suhas BV:
The biggest difference is that a function call cannot block — defining a routine as a function guarantees that it will not block.
Many contexts require that they consume no time, like in the middle of an expression evaluation or the construction of a class. If tasks and functions were merged into one construct, then you would have to analyze the call chain at compile time, or issue a run-time error if encountering a blocking statement. It’s easier to keep the rules, simpler.
In reply to Suhas BV:
is the task will also work at zero simulation if no delays are added,
is there any way we ca call task inside function
Thanks