Hi folks!
I have an issue to import an IP that contains interfaces and structs. The used RTL files are shown as follows:
- interface.sv
interface my_itf
(
input clk
);
logic [7:0] addr;
logic [7:0] data;
modport master(
input clk
, output addr
, output data
);
modport slave(
input clk
, input addr
, input data
);
endinterface
- config.sv
package config;
typedef struct packed {
logic [3:0] header;
logic [63:0] payload;
} pkg_t;
endpackage
- my_module.sv
module my_module
import config::*;
(
input logic rst
, input logic clk
, input pkg_t pkg [4]
, my_itf.master my_itf_if
);
- top.sv
module top
import config::*;
(
...
);
...
// Instantiation
my_module
my_module
(
.rst (rst )
, .clk (clk )
, .pkg (pkg_i )
, .my_itf_if (my_itf_if )
);
So, when I synthesized all files together using “add_files” in Vivado it works like a charm. However, when I created an IP for my_module and added it to my project the synthesis fails, not recognizing the port connections ([Synth 8-11365] for the instance ‘my_module’ of module ‘my_module’ declared at ‘’, named port connection ‘pkg’ does not exist [“top_path”:320])
The workaround was manually changed each port for an array or matrix declaration, such as:
module my_module
import config::*;
(
input logic rst
, input logic clk
, input logic [3:0] pkg_header [4]
, input logic [63:0] pkg_payload [4]
...
);
However, I posted only a simple example. In the real project this workaround is not feasible. So, what is the syntax to instantiate an generated IP with interface and struct in SystemVerilog? Thanks a lot!!!