Can anyone give a good example of RAL and How it’s working?
In reply to big123:
The Verification Academy Advanced Course has everything you need to know about the RAL.
In reply to big123:
Register Abstraction Layer – in my view (based on my observations, maybe formally imperfect) it’s a standard API for reading/writing registers (as someone close to validation) where I don’t need to know the details of the IP and how the buses will really work/be-accessed in Silicon. For designers it gives a standard API/framework for constructing the IP register layout/organization, as well as connecting the standard read/write API calls (like I will use) to whatever different access-methods exist in the design-spec (i.e. the frontdoor ones, which could be JTAG or AHB or APB).