Dear All,
I’m trying to understand about “program block” in Systemverilog. and I’m currently referring this site.
As I see that program block is the same as “module block” in verilog.
So I’m curious what is the purpose of using “program block” in system verilog or drawback?
hi,
module block will sample at active region and executes in the same region.where as program block will sample in active region and executes in reactive region.That's why program block is mainly used in the testbench and module is design.
program block will avoid race conditions,the initial statement in program block will be executed in Reactive region where as initial block of module is executed in active region.
In reply to dave_59:
In reply to sylee:
There is no need to use program blocks. Please see http://go.mentor.com/programblocks
Thanks, Perfectly Cleared.
In reply to dave_59:
Hi Dave,
From SV LRM, 24.4 Eliminating testbench races,
It is important to understand that simply sampling input signals (or setting nonzero skews on
clocking block inputs) does not eliminate the potential for races. Proper input sampling only addresses a single clocking block. With multiple clocks, the arbitrary order in which overlapping or simultaneous clocks are processed is still a potential source for races. The program construct addresses this issue by scheduling its execution in the Reactive region, after all design events have been processed, including clocks driven by nonblocking assignments.
Does it mean that Program block is mandatory while dealing with multiple clocks/clocking blocks ?
In reply to shahkavish77:
No, not at all. RTL designs deal with multiple clocks all the time and there is no need for additional constructs if you understand Verilog semantics,