What is purpose of `true in sv assertion?

SystemVerilog
1

I read it from LRM,but I can’t understand.

2

In reply to sr002:

In the examples in this clause, `true is a Boolean expression that always evaluates to 1’b1 and is used for visual clarity. It is defined as follows:

`define true 1'b1
3

In reply to dave_59:

thanks dave