In reply to Verif Engg:
Quote:
What is the minimum number of test vectors I need to fully verify it it?
Of course, the answer is 2^n. Formal verification will be a good application for this.
Quote:
How do I randomly cover other combinations, like 2 or 3 or 4 inputs set to 1 and vice versa?
You could use something like the following code:
import uvm_pkg::*; `include "uvm_macros.svh"
class C;
rand bit[7:0] s, w;
constraint cs2 {$countones(s)==2; // number on ONEs ==2
};
constraint cw3_zeros {$countones(~w)==3; // Number of ZEROs==3
};
endclass
module top;
bit clk, a, b;
C c;
initial forever #10 clk=!clk;
initial begin
c=new();
repeat(200) begin
@(posedge clk);
if (!randomize(c)) `uvm_error("MYERR", "This is a randomize error")
$display("c.s=%b c.w=%b", c.s, c.w);
end
$stop;
end
endmodule
// simulation results
c.s=00000101 c.w=01101110
# c.s=00100100 c.w=11010110
# c.s=00000011 c.w=00110111
# c.s=00010100 c.w=01101110
# c.s=00110000 c.w=00101111
# c.s=00101000 c.w=11101001
# c.s=10001000 c.w=01111001
# c.s=00001100 c.w=10011011
# c.s=10000001 c.w=01101101
# c.s=01010000 c.w=01111010
# c.s=10001000 c.w=11010011
# c.s=10000100 c.w=00110111
# c.s=10000010 c.w=11100011
# c.s=10100000 c.w=00101111
# c.s=01100000 c.w=00101111
Ben Cohen
http://www.systemverilog.us/
For training, consulting, services: contact
http://cvcblr.com/home
*
SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
*
Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
* Component Design by Example ", 2001 ISBN 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
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