sequence iicByteSeq;
@(posedge clk)
##0 ( 1 [*1:$] ##0 iicBitSeq ) [*9] ;
endsequence
In reply to Subhra Bera:
sequence iicBitSeq;
c ##1 b[*3]; endsequence
sequence iicByteSeq;
@(posedge clk)
##0 ( 1 [*1:$] ##0 iicBitSeq ) [*3] ;
endsequence
// Using 3 instead of $
// (1[*1:3] ##0 iicBitSeq) //is same as
(1[*1] ##0 iicBitSeq) or (1[*2] ##0 iicBitSeq) or (1[*3] ##0 iicBitSeq)
// same as
(##0 iicBitSeq) or (##1 iicBitSeq) or (##2 iicBitSeq)
// NOTE: 1'b1[*2] ##0 b // same as
// (1'b1 ##1 1'b1) ##0 b // same as
// ##1 b // 1'b1 ##0 b // same as b
##0 ( 1 [*1:$] ##0 iicBitSeq ) [*3] // same as
(##0 iicBitSeq) or (##1 iicBitSeq) or (##2 iicBitSeq)
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
In reply to ben@SystemVerilog.us:
Then what is the meaning of this sequnce ?
sequence nackSeq;
##1 1 [*1:$] ##0 $rose(scl) ##0 (iicByteCnt==0&&iicBitCnt==8&&sda&&scl) [*1:$] ##1 !scl;
endsequence
If there is any rule to write this type of sequences then please refer it to me.
In reply to Subhra Bera:
If there is any rule to write this type of sequences then please refer it to me.
Yes, there is a rule: Define the requirements first in English.
// The following sequence
##1 1 [*1:$] ##0 $rose(scl) ##0 (iicByteCnt==0&&iicBitCnt==8&&sda&&scl) [*1:$] ##1 !scl;
// is of the form
##1 1[*1:$] ##0 a ##0 b[*1:$] ##1 c;
// It is poorly written in form because
##1 1[*1:$] ##0 a says that after 1 cycle you wait for an "a".
// Better ways of expressing this include one of the following:
##[1:$] a
##1 a[->1]
// Thus, instead of ##1 1[*1:$] ##0 a ##0 b[*1:$] ##1 c;
##[1:$] a ##0 b[*1:$] ##1 c; //
in a consequent, the assertion can never fail. e.g., isntead of:
w |-> ##[1:$] a ##0 b[*1:$] ##1 c; // CANNOT FAIL
w |-> ##1 a[->1] ##0 b[*1:$] ##1 c; // CAN FAIL
w |-> first_match( ##[1:$] a) ##0 b[*1:$] ##1 c;) Can FAIL, prefer the ##1 a[->1] instead
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115