What is the difference between ## and |=> in assertion?

SystemVerilog
, ,
1

For example if I have following properties and assertions, will the two assertions make any difference?
property prop1;
A ##1 B;
endproperty

property prop2;
A |=> B;
endproperty

A1: assert property (prop1);
A2: assert property (prop2);

2

In reply to rma:

I strongly suggest that you study the concepts of SVA, including the concept of vacuity, and sequence, and properly operators.
There are many books on SVA, including mine, plus lots of information on the web.
Ben systemverilog.us

3

In reply to rma:

The difference is the assertion A1 fails each cycle A is false in addition to the cycles A is true followed the next cycle by B false.

A2 only fails the cycles A is true followed by B false.

4

In reply to dave_59:

thanks. This is what I was trying to get confirmed. I also read some thing about properties like A2 can be matched multiple times. For example, the signals occurs in following ways. AABB at T1T2T3T4, so what is the time for the A2 to be successful? Do you have recommendations about reading materials related to this? How should I refine my knowledge towards those cases? not just superficially understand the syntax, but how/where should I get more complicated usage and examples about SVA?
Thanks a lot.

5

In reply to rma:

http://lmgtfy.com/?q=SVA+implication

As Ben mentioned, there are many SVA textbooks on this subject, probably more than on SystemVerilog as a whole.