What is best way to implement watchdog timer, hash delay or clock based timer

SystemVerilog
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I have checker component and I would like to implement some kind of watchdog timer in that to make sure, at the end of test, I check certain values after clock cycles rather than setting objection and clear objection on events, As implementing those events to clear objection is complicated. so best I can do is if design in certain state , trigger watchdog timer, once timer expires come back and check the values again. To do this
I can setup watchdog_timer_component in clock agent, which can be accessed from any component. (use config db probably).
Every-time checker wants timer based delay it can add timer in watchdog_timer_component and component will callback checker once timer expires.
So question:

  1. is it efficient to do like this as clock based from simulation performance?
  2. instead of counters on posedge in watchdog_timer_component, I can implement Delay based which basically does same as clock period remains constant.

Which is one is bad/good/no affect in terms of simulation performance?

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In reply to vijaybagalad:

Use the phase_ready_to_end method.

See Redirecting…

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In reply to dave_59:
I am doing all above described things in phase_ready_to_end :) More than implementation I wanted to know what is the impact on simulation performace if watchdog is clock based or Delay based.

thanks you.

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In reply to vijaybagalad:

It’s hard to answer that kind of question without looking through your code. It depends on the number of times a process has to wake up in relation to whatever else is going on. Any effort to optimize your code for performance should be accompanied by profiling in your tool.

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In reply to dave_59:

ok thank you Dave, I will try to do that , will post my observation later.

cheers
vijay