What are the differences between these 5 properties in SVA?

SystemVerilog
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1

What are the differences between the 5 properties below in SVA?


property @ (negedge clock) ! Ack|=>ack [*4:5] ##4 ack end_property
property @ (negedge clock) ! Ack|=>ack [=4:5] ##4 ack end_property
property @ (negedge clock) ! Ack|=>ack [->4:5] ##4 ack end_property
property @ (negedge clock) ! Ack|=>ack [4:5] ##4 ack end_property
property @ (negedge clock) ! Ack|=>ack [5:4] ##4 ack end_property
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In reply to VENKATA SATYA VAMSI KRISHNA KESARLA:

The differences are explained in section 16.9.2 Repetition in sequences of the IEEE 1800-2017 LRM, and in many online tutorials.