In reply to dave_59:
In reply to Michael54:
Clocking blocks are certainly optional. There are more useful in poorly written RTL that do not properly use non-blocking assignments in sequential logic, or in gate-level simulations with inaccurate delays.
My DVCon paper "The missing link: the testbench to DUT connection" has a brief mention of them.
Thanks for your answer as always!
I am trying to understand the code provided in the paper of the probe_pkg, and have a few questions:
1. May I use it to retrieve/monitor values of internal RTL signals?
2. Are the signals monitored by this mechanism considered as asynchronous ones (did not see any clocking events/blocks involved)?
3. May I use this "probe" mechanism to monitor Black-Box output single asynchronous signals/buses from my RTL DUT (for example: interrupt/trap signals?)
Thanks in advance!