Warning from QuestaSim

SystemVerilog
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1

I am getting below warning from QuestaSim tool!

(vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.

does anybody know/came accross such warning? I tried to look into QuestaSim userManual but couldnt found any ref. to it?

2

In reply to Vinay Jain:
This is a public forum and not for tool specific issues.

I can tell you that all of the SV always_* constructs have synthesiability checks that require deeper analysis than just syntax checking. So even though your code might complete the first compilation step, there still might be a problem with your code.

3

In reply to dave_59:

Thank you Dave. And yes I know its public fourm, I just want to know if anybody face this kind of warning and help me in getting quicker response. :) Sorry,I wasnt mean to ask tool specific question.