Warning: Cannot use implication in cover property

SystemVerilog
,
1

property p1 (int a);
@ (posedge clk)
disable iff (rstn !== 1’b1)
(sig_c === 1’b1) |-> (int '(sig_d) === a);
endproperty:p1

cover property(p1(5));

Warning:

  1. (rstn !== 1’b1) -----> it is a complex expression
  2. Cannot use implication in cover property? How to resolve this warning. Can I use this (sig_c === 1’b1) ##0 (int '(sig_d) === a);
2

In reply to prateek1219:

This might be a tool specific warning, as there is no such restriction in the LRM.

Your suggested sequence works because there’s no need to guard against failure in a cover directive.