Wait statement in system verilog

SystemVerilog
1

Hi ,

What does wait(0) mean in system Verilog ?
Is it 0 time wait?

Thanks.

2

In reply to as1494:

It means that the person who wrote it either came from writing VHDL, or could not think of a better way to end their process. Since wait(expression) means “suspend this process until the expression become non-zero”, wait(0) means “suspend this process indefinitely”