VSIM not detecting the change in a signal

I have the following code in a UVM Driver:


       while (!driverLogic.done) begin
             
             // Setting the inputs whenever one of the signal changes.
             @(image_if.outCDSCLK2, image_if.outADCCLK)
             
             $display("@ %t (image_if.outCDSCLK2: %b image_if.outADCCLK: %b)",$time,image_if.outCDSCLK2,image_if.outADCCLK);

             // Do stuff
       end

Now, it is my understanding the display statement will NOT be executed unless either outCDSCLK2 or outADCCLK change their value.
So here is what happens at 4953 ns into the simulation I get this printout:

@ 4953 ns (image_if.outCDSCLK2: 0 image_if.outADCCLK: 0)

However this is incorrect. As the simulation CLEARLY shows that at the same time image_if.outCDSCLK2 changes to 1:

This is not a connection problem as the next time outADCLK changes to 1 I get the proper printout:

@ 5078 ns (image_if.outCDSCLK2: 0 image_if.outADCCLK: 1)

Furthermore the @ IS working as in between the last two printouts I get this:

@ 5016 ns (image_if.outCDSCLK2: 0 image_if.outADCCLK: 0)

Which is correct as both signals are 0 and furthermore the value that changed was outADCLK.

So my question becomes, why is this happening? And what can I do to fix it?

In reply to aarelovich:

This is a race condition. Change $display to $strobe, or make sure both outCDSCLK2 and outADCCLK get updated by NBA executing in the same NBA region.