Viterbi decoder output is getting reflected before the inputs are provided

SystemVerilog
1

Hi all,

I have to write a system verilog layered testbench for a viterbi decoder. I have to feed 16 bit input i.e.,d_in, 2 bits each by generating 8 packets such that only after the generation of 8 packets, it should start the traceback and then display the 8 bit output. But while simulating, it starts the traceback after 3 packets and is reflecting incorrect output before the complete 16 bit input is provided.

This is the generator class:

class generator;   
  
  int no_transactions;
  

  bit [1:0]d_in;
  //declaring transaction class  
  transaction trans; 
 //repeat count, to specify number of items to generate 
  int  repeat_count; 
  //mailbox, to generate and send the packet to driver 
  mailbox gen2driv;  
  //event, to indicate the end of transaction generation 
  event ended;  

  //constructor   
  function new(mailbox gen2driv); 
    //getting the mailbox handle from env, in order to share the transaction packet between the generator and driver, the same mailbox is shared between both. 
  //  this.vif = vif;
    this.gen2driv = gen2driv; 
  endfunction 

  //main task, generates(create and randomizes) the repeat_count number of transaction packets and puts into mailbox 
  task main();
    int i  = 0;
    bit [1:0] array_ex [8] ='{2'b11, 2'b01, 2'b10, 2'b01, 2'b00, 2'b01, 2'b01, 2'b11};    
  repeat(repeat_count) begin
      trans = new();
      $display("array : %b",array_ex[i]);
      //@(posedge trans.clk);
      trans.d_in = array_ex[i];
      i++;
    
    trans.display("[ Generator ]"); 
    gen2driv.put(trans);
    no_transactions++;
  end
  -> ended; // triggering indicates the end of generation
endtask
    
endclass

And this is my driver class:

class driver;  


  int no_transactions;   
  
  virtual intf vif;
  mailbox gen2driv,driv2scb;
  
  function new(virtual intf vif,mailbox gen2driv,driv2scb);     
    this.vif = vif;   
    this.gen2driv = gen2driv; 
	   this.driv2scb = driv2scb;
  endfunction   

  
  task rst; 
    wait(vif.rst); 
    $display("[ DRIVER ] ----- Reset Started -----"); 
    vif.th <= 0;  
    vif.d_in <= 0;
    vif.valid <= 0;
    //vif.dec_op <= 0;
    wait(!vif.rst); 
    $display("[ DRIVER ] ----- Reset Ended   -----"); 
  endtask   

  
  task main; 
    forever begin 
      transaction trans; 
      gen2driv.get(trans); 
      @(posedge vif.clk);
      vif.th <= trans.th;
      vif.d_in <= trans.d_in; 
      vif.valid <= 1;
      @(posedge vif.clk);  
      trans.dec_op = vif.dec_op; 
      vif.valid <= 0; 
      @(posedge vif.clk); 
      driv2scb.put(trans);
      trans.display("[ Driver ]"); 
	    no_transactions++;
      end
  endtask
endclass

I am also attaching the image of my waveform:

Any suggestions are greatly appreciated.
Thanks