Virtual Interface

SystemVerilog
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1

Hey,

I am currently studying System Verilog and I got a peculiar question for which I am not sure about the answer.

I know that there is Virtual Interface and we have to use it. What happens if I do not declare the interface as “virtual” and use it? Will i be able to simulate the testbench? I am not sure what impact it does have.

-Sid

2

In reply to srisid:

Hi srisid,
Basically our module is static in nature, and SV TestBench components are dynamic in nature. If your interface is virtual then only we need to access the DUT signals in SV TB.

-Babureddy.