Verilog vs SV

SystemVerilog
1

How to identify the differnce between verilog and system verilog code just by viewing the code?

2

In reply to Design Engineer:

Verilog and SystemVerilog are the same language. There is one IEEE specification that defines the language. SystemVerilog and Verilog were originally defined by two separate standards, but that is no longer the case.

3

In reply to Design Engineer:

Hi,

Until and unless, you find the new keywords/constructs (which belongs to systemverilog) like logic, always_ff, always_comb,enum, struct, definition of functions/tasks without begin/end keywords, threads like join_any, join_none, semaphore (the list continues), you cannot differentiate verilog and systemverilog codes. What ever the program that you have written using verilog keywords can be saved with .v as well as .sv extention.
Hope this helps.
PuttaSatish

4

In reply to cgales:

Thanks @cgales