Verilog code confusion, I do not understand this line of code

SystemVerilog
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read_data = read_address == 4’d8 && y_ff$ETY_N && y_ff$D_O;
What will be the value of “read_data” after this line has been executed? I do not understand whats happening in this line.

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In reply to lala:

We cannot tell you the value of “read_data” without knowing the value of read_address, y_ff$ETY_N, and y_ff$D_O. But it can only be one of three choices 1’b1, 1b0, 1’bx.

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In reply to dave_59:

In reply to lala:
We cannot tell you the value of “read_data” without knowing the value of read_address, y_ff$ETY_N, and y_ff$D_O. But it can only be one of three choices 1’b1, 1b0, 1’bx.

Thankyou Dave. Also can you please explain this part read_address == 4’d8 && y_ff$ETY_N && y_ff$D_O. Example:- A == 4’d8 && B && C taking any example for A, B and C. Also how does this evaluates to either 1’b1, 1’b0 or 1’bx.
Thankyou.

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In reply to lala:

Table 11-21 in the IEEE 1800-2017 SystemVerilog LRM tells you the result of the == and && operators are 1-bit expressions. And table 11-3 gives you the precedence for evaluating these operators.

 D = ( ( (A == 4'd8 ) && B ) && C )
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In reply to dave_59:

In reply to lala:
Table 11-21 in the IEEE 1800-2017 SystemVerilog LRM tells you the result of the == and && operators are 1-bit expressions. And table 11-3 gives you the precedence for evaluating these operators.

 D = ( ( (A == 4'd8 ) && B ) && C )

Thankyou very much Dave. The IEEE Standard for SV book on that link was very helpful, it is a gold for me. The table was also very helpful. I was confused about the result of this ‘==’ operator, I thought its boolean “True or False”, but it turns out to be scalar value 0 for False and 1 for True. BTW I am learning SystemVerilog myself (self learning) and that book will help me alot. Thankyou so much. I really appreciate your help.